gEDA-dev: Re: icarus verilog wor net simulation question

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Lennert Buytenhek wrote:

> 	module blah ( in, out );
> 		input	in;
> 		output	out;
> 
> 		assign out = in;
> 	endmodule
> 
> 	module top;
> 		wor	total;
> 
> 		blah blah1 ( 1'b0, total );
> 		blah blah2 ( 1'b1, total );
> 	endmodule
> 
> Reading the value of blah1.in gives me, confusingly, a 1.


Does Icarus Verilog even support wor? Hmmm, I think it does.
It is possible that it does what you say, I can't tell from
memory. The way to find out is to look at the vvp output.
It appears as you say that in and out wind up wired together
since the assign is acting like a net joint.

It is a little confusing, and maybe even wrong, but the
output is right, and if you drove the ports with non-constant
values you'd get different results.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


_______________________________________________
geda-dev mailing list
geda-dev@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev