gEDA-dev: Re: icarus verilog clock edge at t=0 question

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Lennert Buytenhek wrote:
> Hi,
> 
> Another question (please tell me if I'm being stupid) -- if I
> initialise a register to 1, any sub-modules that I pass this register
> see a posedge at t=0, but the module in which the register is declared
> does not.

You've got a classic time-0 race. Setting clk=1'b1 at time-0
will cause some threads to detect the x-->1 transitions and some
not, simply based on the scheduling of the threads and the initial
assignment. It is common to start the clock toggling some time
after time-0 to avoid this sort of thing.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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