Re: gEDA-dev: Icarus verilog problem with nand

["Chris H" <bitmechanic-at-NOSPAMhotmail_dot_com>]

Hi Steve,

Yes, I'm trying to synthesize. I'm trying to target a library that contains  
NAND and DFF primitives. Ideally, I'm trying to get a EDIF netlist that 
contains only those primitives. I realize I'll need to write a more 
'structural' Verilog, but that's ok. For example I already have modules that 
bulid comparators from NAND gates or counters from NAND gates and DFFs. So, 
being able instantiate a NAND would allow me to do it.

Thanks,
Chris

BTW Icarus verilog is very cool


>From: Stephen Williams <steve@icarus.com>
>Reply-To: gEDA developer mailing list <geda-dev@moria.seul.org>
>To: geda-dev <geda-dev@seul.org>
>Subject: Re: gEDA-dev: Icarus verilog problem with nand
>Date: Wed, 23 May 2007 07:49:46 -0700
>
>Chris H wrote:
> > Hello,
> >
> > I'm trying to instantiate a nand gate in a module, i.e.
> >
> > nand G1 (out1, inA, inB);
> >
> > I'm compiling for synthesis/EDIF output:
> >
> > iverilog -tfpga -parch=lpm -o netlist.edf module1.v module2.v
> >
> > I get errors:
> > UNSUPPORTED LOGIC TYPE: 6
> >
> > I tried other arch also, like -parch=virtex2
> >
> > I'm using version 0.8.4
>
>That just means that the code generator ran into a logic type
>that it doesn't support. (The synthesizer handled it.) The
>code generator for the "fpga" code generator is in tgt-fpga.
>
>Are you really trying to *synthesize* for lpm using Icarus Verilog,
>or are you trying to run a simulation? If the latter, then you
>do not need (or want) the -tfpga flags. If you really are trying
>to synthesize, the the tgt-fpga code generator needs to be fixed.
>
>--
>Steve Williams                "The woods are lovely, dark and deep.
>steve at icarus.com           But I have promises to keep,
>http://www.icarus.com         and lines to code before I sleep,
>http://www.picturel.com       And lines to code before I sleep."
>
>
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