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gEDA-dev: vhd2vl patch and help needed



Hi,

I have been trying to use vhd2vl2.

I have attached a patch with some fixes I have already implemented, but 
I've hit a stumbling block that I can't quite figure out. Please find 
attached the file temp.vhd which is a simplification of the file that 
illustrates the problem. I mention that because I don't know if it's 
really correct VHDL, but it is derived from valid VHDL and 
illustrates/isolates the problem. See below for details on the problem.

List of fixes in patch:

- added 'buffer' and 'inout' types
- added 'nor' logical
- fixed bug in fslprint passing wrong member variable
- fixed "not all paths return a value" bug in copysl()
- added assertsl() and assertsg() functions to validate the contents of 
slists and sglists.
- fixed a couple legacy c compilation issues
- fixed crash in a_decl where range->sizeval wasn't getting set
- fixed crash in edge rule - posedge was returning garbage in $$ which 
was getting passed to addwrap in first edge rule ( the parenthesis rule )
- added NATURAL to wvalue

Here's the problematic line within temp.vhd:

     if (addr-startaddr /= 48) then

Doing this fixes the problem:

     if ((addr-startaddr) /= 48) then

I've learned a LOT about yacc/bison in the last few days while going 
through all this stuff, but this particular problem is beyond me. I've 
studied the grammar and the output file and run the parser with the -d 
option, and I just can't seem to isolate where the problem is. It looks 
like it should work to me.

This is how I believe it *should* be breaking it down, in case that helps:
exprc ->(130)-> conf
conf ->(141)-> expr /= expr
1st expr ->(117)-> expr - expr
both expr ->(108)-> signal

Thanks for any assistance you might consider lending on this problem.
--- vhd2vl.orig.l	Fri Jun 16 13:21:12 2006
+++ vhd2vl.l	Sun Jul 08 12:53:44 2007
@@ -21,6 +21,8 @@
     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 
+%option noyywrap
+
 %{
 #include <stdio.h>
 #include <string.h>
@@ -67,6 +69,8 @@
 "map" { return MAP; }
 "in" { return IN; }
 "out" { return OUT; }
+"buffer" { return BUFFER; }
+"inout" { return INOUT; }
 "time" |
 "natural" |
 "integer" |
@@ -90,8 +94,7 @@
 "not" { return NOT; }
 "when" { return WHEN; }
 "exit" { return EXIT; }
-"with" {
-  return WITH; }
+"with" { return WITH; }
 "select" { return SELECT; }
 "others" { return OTHERS; }
 "range" { return RANGE; }
--- vhd2vl.orig.y	Fri Jun 16 13:20:44 2006
+++ vhd2vl.y	Sun Jul 08 14:54:20 2007
@@ -22,11 +22,16 @@
 */
 
 %{
+int yydebug=1;
 #include <stdio.h>
 #include <string.h>
+#include <stdlib.h>
+#include <malloc.h>
 #include <assert.h>
 #include "def.h"
 
+#define malloc(n) calloc(1,n)
+
 int skipRem = 0;
 int lineno=1;
 
@@ -53,6 +58,35 @@
 int indent=0;
 slist *indents[MAXINDENT];
 
+void assertsl(slist *sl)
+{
+  int i;
+  if(sl){
+    assert ( (unsigned)sl != 0xcdcdcdcd );
+    assert(sl != sl->slst);
+
+    assertsl(sl->slst);
+    switch(sl->type){
+    case 0 :
+      assert(sl != sl->data.sl);
+      assertsl(sl->data.sl);
+      break;
+    case 1 : case 4 :
+      assert ( sl->data.txt && (unsigned)sl->data.txt != 0xcdcdcdcd );
+      for ( i = 0; sl->data.txt[i]; i++ )
+        assert ( sl->data.txt[i] > 0 );
+      break;
+    case 2 :
+      break;
+    case 3 :
+      assert ( sl->data.ptxt && (unsigned)sl->data.ptxt != 0xcdcdcdcd );
+      assert ( *sl->data.ptxt && (unsigned)*sl->data.ptxt != 0xcdcdcdcd );
+      break;
+    }
+  }
+}
+
+
 void slprint(slist *sl){
   if(sl){
     assert(sl != sl->slst);
@@ -91,7 +125,7 @@
       fprintf(fp,"%d",sl->data.val);
       break;
     case 3 :
-      fprintf(fp,"%s",*(sl->data.txt));
+      fprintf(fp,"%s",*(sl->data.ptxt));
       break;
     }
   }
@@ -120,6 +154,7 @@
     }
     return newsl;
   }
+  return NULL;
 }
 
 slist *addtxt(slist *sl, char *s){
@@ -212,13 +247,45 @@
   return sl;
 }
 
-slist *addwrap(char *l,slist *sl,char *r){
-slist *s;
+slist *addwrap(char *l,slist *sl,char *r)
+{
+  slist *s;
   s=addtxt(NULL,l);
   s=addsl(s,sl);
   return addtxt(s,r);
 }
 
+void assertsg ( sglist* sg, int line )
+{
+#if 0
+  fprintf ( stderr,"assertsg (%i):\n", line );
+  while ( sg )
+  {
+    fprintf(stderr,"  %s TYPE: %s VTYPE: ",sg->name,sg->type);
+    switch ( sg->range->vtype )
+    {
+    case tSCALAR:
+      fprintf ( stderr, "SCALAR" );
+      break;
+    case tSUBSCRIPT:
+      fprintf ( stderr, "SUBSCRIPT" );
+      break;
+    case tVRANGE:
+      fprintf ( stderr, "VRANGE" );
+      break;
+    default:
+      fprintf ( stderr, "??? (%i)", sg->range->vtype );
+    }
+    fprintf ( stderr, " SIZEVAL: %i  SIZE_EXPR: ", sg->range->sizeval );
+    fslprint ( stderr,sg->range->size_expr);
+    fprintf ( stderr, " NLO: " ); fslprint ( stderr, sg->range->nlo );
+    fprintf ( stderr, " NHI:"); fslprint ( stderr, sg->range->nhi );
+    fprintf ( stderr, "\n" );
+    sg = sg->next;
+  }
+#endif
+}
+
 sglist *lookup(sglist *sg,char *s){
   for(;;){
     if(sg == NULL || strcmp(sg->name,s)==0)
@@ -383,9 +450,9 @@
     }  /* if(sg) */
   }
   if (!useExpr) {
+    slist *p;
     assert(size>0);
     /* use size */
-    slist *p;
     p = addval(NULL,size);
     fixothers(p,sl);
   }
@@ -403,14 +470,14 @@
   slval *ss;  /* Signal structure */
 }
 
-%token <txt> REM ENTITY IS PORT GENERIC IN OUT MAP
+%token <txt> REM ENTITY IS PORT GENERIC IN OUT BUFFER INOUT MAP
 %token <txt> BIT BITVECT DOWNTO TO TYPE END
 %token <txt> ARCHITECTURE COMPONENT OF
 %token <txt> SIGNAL BEGN NOT WHEN WITH EXIT
 %token <txt> SELECT OTHERS PROCESS VARIABLE CONSTANT
 %token <txt> IF THEN ELSIF ELSE CASE
 %token <txt> FOR LOOP GENERATE
-%token <txt> AFTER AND OR XOR MOD UNIT
+%token <txt> AFTER AND OR NOR XOR MOD UNIT
 %token <txt> LASTVALUE EVENT POSEDGE NEGEDGE
 %token <txt> STRING NAME RANGE NULLV
 %token <txt> CONVFUNC_2 BASED
@@ -437,9 +504,11 @@
 %right '='
 /* Logic operators: */
 %left ORL
+%left NORL
 %left ANDL
 /* Binary operators: */
 %left OR
+%left NOR
 %left XOR
 %left AND
 %left MOD
@@ -678,10 +747,12 @@
             sglist *p;
 
               if(dolist){
-                if($3)
-                  sl=addtxt(NULL,"output");
-                else
-                  sl=addtxt(NULL,"input");
+                switch ( $3 )
+                {
+                case 0: sl = addtxt(NULL,"output"); break;
+                case 1: sl = addtxt(NULL,"input"); break;
+                case 2: sl = addtxt(NULL,"inout"); break;
+                }
 
                 sl=addpar(sl,$4);
                 p=$1;
@@ -712,10 +783,12 @@
             sglist *p;
 
               if(dolist){
-                if($3)
-                  sl=addtxt(NULL,"output");
-                else
-                  sl=addtxt(NULL,"input");
+                switch ( $3 )
+                {
+                case 0: sl = addtxt(NULL,"output"); break;
+                case 1: sl = addtxt(NULL,"input"); break;
+                case 2: sl = addtxt(NULL,"inout"); break;
+                }
 
                 sl=addpar(sl,$4);
                 p=$1;
@@ -748,6 +821,8 @@
 
 dir         : IN { $$=0;}
             | OUT { $$=1; }
+            | BUFFER { $$=1; }
+            | INOUT { $$=2; }
             ;
 
 type        : BIT {
@@ -816,9 +891,9 @@
               $$->nlo=$1->sl;
           }
           | NAME '\'' RANGE {
+              sglist *sg = NULL;
               /* lookup NAME and copy its vrange */
               $$=(vrange *) malloc(sizeof(vrange));
-              sglist *sg = NULL;
               if((sg=lookup(io_list,$1))==NULL) {
                 sg=lookup(sig_list,$1);
               }
@@ -936,6 +1011,7 @@
               $$=addsl(sl,$9);
               p=(sglist *) malloc(sizeof(sglist));
               p->name=$3;
+              p->type="type";
               p->range=(vrange *) malloc(sizeof(vrange));
               p->range->nlo=addtxt(NULL,"0");
               if(k>0) {
@@ -943,6 +1019,7 @@
                 p->range->vtype = tVRANGE;
                 sprintf(natval, "%d",k);
                 p->range->nhi=addtxt(NULL,natval);
+                p->range->sizeval = k+1;
               } else {
                 p->range->vtype = tSCALAR;
                 p->range->nhi= NULL;
@@ -1303,19 +1380,23 @@
      | NAME '\'' EVENT AND exprc {
          clkedges[clkptr++]=$5->data.sl->data.txt[0]-'0';
          assert(clkptr < MAXEDGES);
+         $$ = NULL;
        }
      | exprc AND NAME '\'' EVENT {
          clkedges[clkptr++]=$1->data.sl->data.txt[0]-'0';
          clkptr++;
          assert(clkptr < MAXEDGES);
+         $$ = NULL;
        }
      | POSEDGE '(' NAME ')' {
          clkedges[clkptr++]=1;
          assert(clkptr < MAXEDGES);
+         $$ = NULL;
        }
      | NEGEDGE '(' NAME ')' {
          clkedges[clkptr++]=0;
          assert(clkptr < MAXEDGES);
+         $$ = NULL;
        }
      ;
 
@@ -1586,6 +1667,7 @@
 
 wvalue : STRING {$$=addvec(NULL,$1);}
        | NAME {$$=addtxt(NULL,$1);}
+       | NATURAL {$$=addval(NULL,$1);}
        ;
 
 sign_list : signal {$$=$1->sl; free($1);}
@@ -1796,6 +1878,7 @@
      | NOT expr {$$=addexpr(NULL,'~'," ~",$2);}
      | expr AND expr {$$=addexpr($1,'&'," & ",$3);}
      | expr OR expr {$$=addexpr($1,'|'," | ",$3);}
+     | expr NOR expr {$$=addexpr(NULL,'~'," ~",addexpr($1,'|'," | ",$3));}
      | expr XOR expr {$$=addexpr($1,'^'," ^ ",$3);}
      | BITVECT '(' expr ')' {
        /* single argument type conversion function e.g. std_ulogic_vector(x) */
@@ -1856,6 +1939,12 @@
           sl=addtxt($1," || ");
           $$=addsl(sl,$3);
         }
+      | exprc NOR exprc %prec NORL {
+          slist *sl;
+          sl=addtxt($1," || ");
+          sl=addsl(sl,$3);
+          $$=addwrap("~(",sl,")");
+        }
       | NOT exprc %prec NOTL {
         slist *sl;
           sl=addtxt(NULL,"!");
@@ -1985,8 +2074,8 @@
       }
      | NATURAL {
          expdata *e;
-         e=(expdata *) malloc(sizeof(expdata));
          char *natval = (char *) malloc(99*sizeof(char));
+         e=(expdata *) malloc(sizeof(expdata));
          e->op='n'; /* natural */
          e->value=$1;
          sprintf(natval, "%d",$1);
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity temp is
  port(
    triIDvalid : out std_logic;
    clk : in std_logic );
end;

architecture rtl of temp is

  signal addr,startAddr : std_logic_vector(11 downto 0);
begin

  Process(clk)
  begin
    if (rising_edge(clk)) then
      if (addr-startaddr /= 48) then
        triIDvalid <= '1';
      end if;
    end if;
  end process;
end rtl;


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