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gEDA-dev: Icarus Verilog command file
In a command file (the argument to the -c flag) I have
/home/alan/Sun/OpenSPARCT2.1.0beta/design/sys/iop/cpu/rtl/cpu.v
$DV_ROOT/design/sys/iop/ccx/rtl/ccx.v
...
The value of the DV_ROOT environment variable is
/home/alan/Sun/OpenSPARCT2.1.0beta
iverilog doesn't complain about the first Verilog source file, but for
the second one it reports
$DV_ROOT/design/sys/iop/ccx/rtl/ccx.v: No such file or directory
ccx.v does, in fact, exist.
The iverilog man page claims that "Variables are substitued in file
names." Therefore, $DV_ROOT should have been understood, right? Isn't
that what that means?
--
Alan Feldstein
Cosmic Horizon logo
http://www.alanfeldstein.com/
+1 585 415 6682
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