Re: gEDA-dev: Faster PCB + GL

[Peter Clifton <pcjc2-at-NOSPAMcam_dot_ac_dot_uk>]

On Sun, 2008-06-22 at 16:21 -0400, Joshua Boyd wrote:
> On Sun, Jun 22, 2008 at 05:55:21PM +0100, Peter Clifton wrote:
> 
> > Part of that speedup over the stock PCB case is due to the caching of
> > diced polygons. It doesn't quite work yet (not updating the cached
> > outlines when it should). If I get chance, I'll see what the rendering
> > rates of stock PCB look like with just those changes.
> 
> Might the caching be fed back into non-OpenGL versions in a way that
> several of the HID variants could benefit from it?
>  
> > I'm not sure how any of these different approaches stand with the
> > possibility of anti-aliased geometry, but I find it absence less of a
> > visual problem than in gschem. (Must finish the cairo work at some
> > point). I'll also have a poke at anti-aliasing techniques for OpenGL.
> 
> I think you just need
>  glEnable(GL_POLYGON_SMOOTH);
> 
> However, 
>  glHint(GL_POLYGON_SMOOTH_HINT, [GL_FASTEST, GL_NICEST, or GL_DONT_CARE]);
> may also be helpful.

Does that affect triangle primitives as well? I see there is an
equivalent GL_LINE_SMOOTH and GL_POINT_SMOOTH.

When I tried the above, I couldn't notice any difference in output, and
didn't see any of the line-edges (2x triangles per line + caps) being
anti-aliased.

> And there may be some driver override in effect.  At least, I think I've
> seen that in the Windows control panels, so I don't know if that means
> there would be also Xorg settings to override software choices in this
> area. 

I wouldn't know where to look, but I don't recall having seen anything
like that (at least not for the Intel driver).

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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