Re: gEDA-dev: PCB plugin for rat selection

[Peter Clifton <pcjc2-at-NOSPAMcam_dot_ac_dot_uk>]

On Mon, 2008-11-10 at 07:58 +0100, Bert Timmerman wrote:

> Expanding on this line of thought:
> 
> Maybe it would be useful to have a feature in pcb to set the clearance
> of an entire track (on a per net basis).
> This because of the entire net carrying the same (high) potential
> (voltage) which needs the same clearance w.r.t. adjoining
> traces/polygons.

+1 on the idea, and basic implementation

To really nail this feature for high-voltage or line-connected work, we
probably need a much more complete DRC check for creepage and clearance
(obviously we can only do this for the board alone - not when fitted
with components).

On a rectified line AC-DC circuit, I might need "x" clearance between my
B+, or 330V DC line, and the DC- (or nominal 0V) rail. However, I might
not need nearly as much clearance for the tracks of some sensing element
or circuit which is referred to the DC+ rail. (Since this is fed via a
bridge rectifier from the mains, the "DC- or nominal 0V" line is still
live and dangerous w.r.t chassis earth, and needs clearance to that..)

I'm not an expert here, so am not familiar with all the nuances, and
practicalities, but appropriate spacing is something I've had to read up
on when designing voltage sensing boards for power converters.


Anyway... the point I'm getting at, is that the clearances in the
general case need to be based on maximum nominal net-net voltages. As a
further complexity, the class of insulation required varies net-net, or
net-group to net-group. Different insulation classes will required
different creepage / clearance distances for a given voltage.

For example, when designing a line-connected supply, you have to meet
particular safety isolation requirements between the line-connected and
isolated portions of the circuit, in addition to providing good
functional insulation between all circuits.

I'd love to have a DRC which could check the resulting PCB for any
subtle mistakes on this issue. It could also function as a guide whilst
routing (e.g. auto-enforce-DRC-rules), even better.


-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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