Re: gEDA-dev: Last call for input on SOW for Linux Fund....

["Svenn Are Bjerkem" <svenn_dot_bjerkem-at-NOSPAMgooglemail_dot_com>]

On Thu, Dec 4, 2008 at 9:53 PM, John Doty <jpd@noqsi.com> wrote:
>
> On Dec 3, 2008, at 5:26 PM, Dan McMahill wrote:
>
>> John Doty wrote:
>>> On Dec 3, 2008, at 7:40 AM, Svenn Are Bjerkem wrote:
>>>
>>>> Ken Kundert knows what he is talking about
>>>
>>> I don't think so. He thinks mixed-signal design is like computer
>>> programming. But it's not: to do it well you have to start from the
>>> *physics* of what you're trying to accomplish.
>>
>> I guess thats why a huge number of complex commercial chips are
>> verified
>> using the simulator that Ken designed?
>
> Of what sort? Can you name an actual chip? There Verilog-AMS culture
> seems to be about making extravagant claims which can never be
> evaluated. The physical reality is always hidden in the fog. But
> simulation isn't the issue here anyway: it's the claim that the
> utility of Verilog-AMS goes beyond simulation.

"Going beyond simulation" very much sounds like marketing, yes, but
what is exactly the meaning of going beyond simulation? Use of
Verilog-AMS as an interchange format? As both Verilog and VHDL can
describe the structure of a circuit, that is possible, at least down
to a certain level, but is it feasible to replace SPICE as an
interchange netlist format with Verilog or VHDL? That depends on the
tools that read the netlists. The extra information given in a VHDL
file must also not only be readable, but also understandable by the
software reading it.

In spice, the model is a part of the simulator. In your spice deck,
you only provide the simulator with parameters to those models. With
AMS, you rip the models out of the simulator and provide them as a
part of your deck. This means that your AMS netlist will be
self-contained both regarding to digital and analog. We all know that
digital can be synthesised from a high level description. That's not
the same with analog _*currently*_. To make analog synthesis happen,
you first have to rip the model descriptions of analog out of the
simulator and make it so generic that any tool can read them and
analyse them in a mathematical correct way. The analog synthesiser
must have math and parameters to be able to do anything useful. Thsi
first step has been done: Both Verilog and VHDL have AMS descriptions
standardised. Now it is up to the clever brains to do the rest. *Then*
they will go "beyond simulation".

> You can write computer programs from the top down in ignorance of the
> physical implementation of the computer. You cannot do this
> effectively with mixed signal design, because the physics of the low-
> level parts is profoundly important.

It's not about either top-down or bottom-up; it is about making *both*
happen, if possible at the same time. System design is typically
top-down, layout is typically bottom-up and implementation is anarchy
depending on how large the design group is. The problem is not the
design, it is the verification that the design is actually working,
that signal levels are correct on the boundaries between analog and
digital. Compilers have made the hardware architecture of a computer
transparent to the coder, just like synthesisers have made digital
design transparent. Just as digital synthesisers took a long time to
mature, analog synthesisers will take even longer as their modus
operandi is continous and not discreete. The actual physics of what
you want to implement still has to be understood to have a successful
implementation, and even with synthesisers (or compilers) there may be
parts of a circuit (program) that needs to be hand-optimised to reach
performance.

> But what Horowitz understands is that the physical fundamentals are
> keys in the mixed-signal domain. Kundert does not seem to understand
> this.

I look at Horowitz as a system designer, he knows what should be the
result of his work, because he defines the work through a
specification based on what he wants to happen. Kundert offers a tool
that make Horowitz able to give that specification to another person
to have the actual circuit designed. Designing a circuit from spec is
a different task than writing the spec. As a system designer, Horowitz
can also introduce concepts of implementation into his spec in order
to help or steer the implementation. These concepts are often verified
with tools like Matlab to investigate resulting noise, dynamic range
and power. Now, Matlab does not know very much about semiconductor
physics, so it can only verify that one concept is "conceptually"
better than another concept. If Matlab would understand an AMS
description, you could even verify the result you would get on the
chip depending on how good you write the models. The models would then
be the same for Matlab and the chip simulator. That's not possible
today as most models are hard-compiled into the simulator, and the
simulator does a lot of tricks behind the scene to speed the
simulation.

>>   But for the IC industry
>> which is really where Verilog-{HDL,A,AMS} are used, simulation
>> tools are
>> critical and those 3 in particular fill a critical need.
>
> But what got me started on this thread is Al's claim that the
> capabilities of Verilog-AMS go beyond simulation to supporting a
> general-purpose interchange format. This seems a pretty wild claim:
> where's at least a toy example? Kundert makes an equally unsupported
> claim: that software-oriented top-down design is a sensible approach
> for mixed-signal circuits.

My toy example is Matlab being able to understand AMS description and
extract whatever information it needs to understand the system better.
Maybe the whole AMS thing could be thought about in the context of
XML: Take what you need and leave the rest as it is. What you don't
understand, you ignore, but please don't destroy it, some other tool
may need it. If you add something, then please add it according to
rules so that other tools that need your information can read and
understand it.

That way, an AMS netlist can go back and forth through the whole
design chain from specification to layout and production. If done
right, it is not important where the AMS netlist starts its life. That
way you could start designing your physical interfaces and then go
back to top. AMS is a tool primarily for teams. As a single designer
you will not be waiting for the work of other to finish anyway. Maybe
that is something to consider also.

> OK, so you use it as a reference manual for a programming language
> for simulation. That's not what Kundert is selling: he wants you to
> be designing your circuits with it. And it's not what Al is selling:
> he wants you to represent your schematics and layouts with it. All
> this selling...

John, you are selling: "Let's stay with things as they are because
that is what I understand". If that makes you happy, fine, but Kundert
tries to tell about a different concept and he has an audience. Al's
audience is a bit smaller, but his concept is to have everything
represented within the same circuit description file. It may be
possible to do so with Verilog or VHDL, but the question is how much
momentum can be gathered to make that happen. If we want analog
synthesis to have a chance to happen, the models must out of the
simulator and into the "deck".

>
>>   In contrast I have not reached
>> for the Horowitz book since sophomore or junior in college 2
>> decades ago.
>
> What do you read when you need to refresh your knowledge of the
> physical foundations?

The latest revision of Tietze & Schenk in German. There is also an
English version available, ISBN 978-3-540-00429-5

> Oh, I use various techniques. Analog computer simulations in SPICE
> are easy and not subject to physical limitations. Mathematica is a
> powerful tool because it allows mixtures of symbiolic and numerical
> analysis, so, for example, I can find the time constants for critical
> damping easily.

With SPICE you will have to limit your model to the elements that
SPICE provides you with. No question, you can generate loads of
complex models of the available elements. If you want to generate a
new model for a semiconductor device, say you are working on bsim50,
you will not be able to simulate very large circuits with your spice
made models. Compiled-in models are faster than Verilog-A models, but
Verilog-A is much faster than custom made "models" in SPICE. And they
are easier to parametrize. Maybe not the thing a silicon designer does
every day, but there are cases where ad-hoc models would be nice. Say
when you try to use a process normally used for analog (and hence only
properly modelled for analog behaviour) for switching purposes. GaAs
and GaN are processes where a digital behaviour is not nescessarily
well modelled. If you have a math crack in your team, then it is a
question of time before you will have a more proper digital model for
digital GaN, and with Verilog-AMS you would be able to test your model
and concept.

> Million dollar mask set? That's got to be nearly all digital, no?

It just has to be node size less 90 nm, then about any mask set will
reach that sum. Pure analog circuits rest at 180 nm or 110 nm.
Anything smaller tends to move into the area of statistical
probabilities. But when you want a little analog join a huge portion
of digital, sometimes you have to cram that analog onto the same die
as the digital, and then you have a problem as an analog designer. You
simply don't have the verification tools like the digital guys have to
verify that your circuit is working at all corners. And if you cannot
simulate analog and digital alongside somehow, your design will be
more or less doomed. I've seen respins happen because the crossings
between analog and digital domain were not simulated together.

> SPICE. And the only time I've had that (partially) fail was when the
> mask set the layout contractor sent to MOSIS was different from what
> they used to extract the netlist for my final sims. A major screwup,
> but "garbage in, garbage out". A better simulator wouldn't have helped.

But maybe a self-contained netlist would have?

> It's a balancing act. I've cut back some on sims for my more recent
> designs because the time to set them up and interpret the results was
> costing more than a 40 chip run.

Most designs do not have this kind of boundaries. A respin takes time
if you have to go for a full mask redesign, and time to market is
something which should not be forgotten as a parameter in the
discussion.

-- 
Svenn


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