Re: gEDA-dev: Last call for input on SOW for Linux Fund....

[John Doty <jpd-at-NOSPAMnoqsi_dot_com>]

On Dec 4, 2008, at 5:47 PM, r wrote:

> This discussion is getting long and probably a bit off-topic but the
> problem is so interesting I can't resist to add a comment. ;-)
>
> As a mixed-signal designer I do not find verilog-ams particularly
> useful as a design description language. And yes, I am working on very
> complex mixed-signal circuits, which are used in even more complex
> systems.

OK, this makes sense. It is the idea that it can represent more than  
just simulation that mystifies me.

>
> What IMHO vams is designed for is functional _digital_ simulation. A
> mixed-signal or analog designer makes a simplified functional model of
> his circuit (preferably before starting work on the transistor level
> design) so that a digital designer can plug it into his system and see
> if all bits are connected correctly. That's probably main reason why
> mixed-signal simulators moved from analog simulators with a digital
> plugin to digital simulators with analog plugins.

In my world (astrophysical instrumentation), at least, the complexity  
of analog circuits doesn't seem to change much over the decades. They  
shrink, get faster, and use less power, but they don't get a lot more  
complicated. It's on the digital side where the complexity grows. So  
again, this makes sense.

> This is btw very
> similar to the System-C story, which is mainly about giving software
> designers a bigger picture of the system.
>
> It doesn't mean I am not using mixed-signal simulators. I use them
> quite a lot but probably not quite the way their designers expected me
> to do it. For me, vams is mostly a great design instrumentation tool.
> For this reason I would prefer vams to be more transparent, to permit
> breaking design encapsulation rules etc (just like debuggers do -
> nobody complains that gdb permits looking into local variables etc.).

So you take the view that vams is a more flexible simulator for IC  
design specialists. Fair enough: that's a sensible and moderate  
position.

Dan privately sent me a list of chips where vams was an important  
tool for simulation during design. Interestingly, if you go to that  
manufacturer's web site, there are no Verilog models at all: SPICE  
rules. Go figure.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@noqsi.com




_______________________________________________
geda-dev mailing list
geda-dev@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev