[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: gEDA: iSDF



On Fri, Jan 04, 2002 at 08:26:44AM -0800, Steve Wilson wrote:
> If someone can do a place & route in a Xilinx of a simple example, maybe a
> flip/flop or two - perhaps a counter I would LOVE to add it to the test
> suite!!!

I can do a a test route on Monday. Does the design need to be synthesised 
with ivl for annotation to work (is that working?)?

I don't know Verilog though :-) Send me an EDIF or XNF and I can route
it though. Or if synthesis tool doesn't matter, just send me the Verilog
code.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>