Re: gEDA: iSDF

[Stephan Boettcher <stephan-at-NOSPAMnevis_dot_columbia_dot_edu>]

Hi!

Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes:

> I'd appreciate a short guide how to use iSDF, e.g example command lines
> and/or perhaps an annotated test suite. 

Patience please.  I will make some simple tests and examples, README, etc.  

My own test case is a standard cell ASIC.  The SDF is 2.7 MBytes,
made by Pearl (Cadence), from an RSPF made by Silicon Ensemble.  The
netlist was synthesised by Synopsys.

> For example the Quicklogic place and route tool emits these SDF
> files for post-placement timing analysis, and I hope to (in the long
> run) be able to use icarus/isdf for post-layout simulation. Is this
> the intention of isdf?

I don't know about Quicklogik, but I guess this is exactly the
intention of isdf :-)


Steve Wilson <stevew@intrinsix.com> writes:

> If someone can do a place & route in a Xilinx of a simple example, maybe a
> flip/flop or two - perhaps a counter I would LOVE to add it to the test
> suite!!!

Before we add tests to the testsuite, I should think about how to host
this project, and/or discuss with Stephen how to integrate it with
Icarus Verilog.


Hamish Moffatt <hamish@debian.org> writes:

> I can do a a test route on Monday. Does the design need to be synthesised 
> with ivl for annotation to work (is that working?)?

The design does not need to be synthesised with ivl.  The cell models
must be modules, which instantiate only gates and UDPs.  

The annotation does not use/need any specify blocks in the models,
specify blocks are parsed by IVL, and otherwise ignored.

$sdf_annotate("file.sdf", scope)  reads the sdf file, and tries to
implement all iopath and interconnect delays in `scope'.  `scope' must
be the instance name of the design in the testbench. 

$sdf_annotate() should be called before $dumpvars() or other callback
generators, since future releases of iSDF will actually connect the
callbacks to the interconnect-delayed input signals :-)

   module test;
      my_design dut (ports);
      initial
         begin
            $sdf_annotate("my_design.sdf", dut);
            $dumpvars;
         end
   endmodule

Compile with

   iverilog -m sdf

How does it work:

Interconnect delay specifications add delay functors to the vvp
functor netlist, between the driver of the signal, and any functor
inputs that are inside the scope of the target input port.

IOpath delays connect timing functors to module input ports.  When a
transition is detected, the delay value of the functor that drives the
module output port is modified.  Conditions are not yet supported, but
should be relatively easy to add.

This is all not perfect, but should somewhat cover most typical cases.

Cheers
Stephan

-- 
Stephan Böttcher                  FAX: +49-4181-925676
Itzenbütteler Straße 130          Tel: +49-4181-32582
21266 Jesteburg                   mailto:stephan@nevis.columbia.edu
Germany                           http://www.nevis.columbia.edu/~stephan