Re: gEDA: netlisting a heirachal netlist

["Mike Jarabek" <mjarabek-at-NOSPAMistop_dot_com>]

Stephen <stephen@elantec.com> said:

> Heirachical netlisting should be a fundamental part of a netlister.
> Heirachical netlists are far more useful in the EDA world than flat
netlists.
> This should be a definite addition for a future release.
> I would have thought it was easier to code anyway as you don't have to make
> heirachical net names.

As I side note, hierarchical netlisting works with both the Verilog and VHDL
backends, although not `automaticcally' (i.e. many shematics -> many hdl
modules in one step, more like schematics->one hdl module, you need a Makefile
or script to re-run the netlister once per module, not too onerous).  IMHO, I
suspect that the missing hierarchy in the Spice netlister is due to the way
that spice records are output, and that there isn't (yet) a well defined way
of specifiying that symbol-x represents a subckt. (Is there?)

Mike

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