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Re: gEDA: iSDF
Hallo,
iSDF version 0.1 is available at
http://www.nevis.columbia.edu/~stephan/sdf.tar.gz
iSDF is an SDF timing annotator for the Icarus Verilog VVP simulation
engine.
This version adds support for a few timing checks (setup, hold,
width).
The tarball includes an example design: example/lfsr/, with an SDF
file generated by the Pearl static timing analysis tool, from a RSPF
parasitics file genereted from Silicon Ensemble ASIC place and route
tool (Cadence). Contributions of examples from different tools are
appreciated.
iSDF is dynamically linked to the vvp simulation engine, which does
not work on Windows platforms, without some trickery. After some
discussions with Stephen Williams, we decided to postpone support for
Windows until after I settled with my family in our new home and job.
iSDF is Linux/Unix only, for now. Sorry.
iSDF no longer requires any patches to Icarus Verilog from Steve's CVS
repository. The latest snapshot and the upcoming 0.6 release should
work as well.
Cheers
Stephan
2001-01-21: version 0.1
Timingchecks SETUP, HOLD, and WIDTH.
Avoid direct calls to vvp_delay_t constructors.
2002-01-06: version 0.0.2
$(ivldir) set by configure.
./examples/lfsr/ added.
2002-01-05: version 0.0.1
Added a few doc files.
Fixed two complaints by Stephen:
vvp_printf() --> vpi_mcd_printf()
NULL delays must not execute methods (->size())
--
Stephan Böttcher FAX: +49-4181-925676
Itzenbütteler Straße 130 Tel: +49-4181-32582
21266 Jesteburg mailto:stephan@nevis.columbia.edu
Germany http://www.nevis.columbia.edu/~stephan