gEDA: Verilog netlister bug corrected.

[Mike Jarabek <mjarabek-at-NOSPAMistop_dot_com>]

Hi all,

    Freshly committed to CVS is a fix for the Verilog netlister.  If you 
had a symbol with a pin labled with, say, `A[15:0]', the netlister would 
list this in a sub block instantiation named port as `.A[15:0] ( B[15:0] 
)'.  This is a Verilog syntax error.  The change I just commited strips 
any bit-selects off the identifier before outputting it, so now the 
output will look like this: `.A ( B[15:0] )' which is now legal Verilog.

    We discovered this after the guys here had created dozens of symbols 
with pins named this way, and were having the Verilog simulator complain 
about syntax.

Mike Jarabek

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                              Mike Jarabek
                                FPGA/ASIC Designer
 http://www.istop.com/~mjarabek
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