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RE: gEDA: LPM as a generic architecture

Hi Brian,

Consider using FNF - it's an extremely simple netlist format designed specifically for RTL analysis.  I recently finished an Icarus FNF code generator, and InFormal, a tool which reads in FNF and PSL and writes out FNF, NuSMV, and synthesizable Verilog.

  http://www.confluent.org/wiki/doku.php?id=fnf:main
  http://www.confluent.org/wiki/doku.php?id=informal:main

-Tom



-----Original Message-----
From: owner-geda-dev@seul.org [mailto:owner-geda-dev@seul.org]On Behalf
Of Brian Greskamp
Sent: Wednesday, December 08, 2004 3:30 PM
To: geda-dev@seul.org
Subject: gEDA: LPM as a generic architecture


I'm designing a tool to analyze the dataflow of synthesized Verilog / 
VHDL designs and I was considering using EDIF / LPM as the input format 
for the tool.  It's ideal for me because the level of abstraction I need 
(i.e. "mux", "register, "add") is intact in LPM.  When targeting a 
specific FPGA or ASIC, the synthesis output is much lower level (LUTs, 
FFs, etc.)

I was glad to find that Icarus is in the process of adding an LPM 
synthesis target.  I assumed commercial synthesizers would also have LPM 
targets.  Unfortunately, I've RTFM for several (Leonardo, Synopsys, 
Xilinx ISE) and can't find any reference to LPM except that they allow 
instantiation of LPM components in a design.

So do any synthesizers other than Icarus target LPM?  Are there other 
architecture-independent targets that are better supported?

Thanks,
Brian