Re: gEDA: Need help resolving a scheduling contradiction

[geda-at-NOSPAMgrfx_dot_com]

> 
> On Wed, 29 Jun 2005 geda@grfx.com wrote:
> 
> > There is (IMO) a slight problem with the view that it's OK to treat
> > a continous assign the same way as a gate: while it makes sense for
> > the case of "wire x = y & z", the degenerate case of "wire x = w" is
> > perfectly realizable in hardware as a short-circuit and as such it
> > shouldn't incur ANY scheduling delay (and thereby race conditions).
> 
> If wires in Verilog are unidirectional, they function more like buf gates,
> not short circuits.  Force x in the PLI and w will keep its old value.
> 
> -t

The unidirectionality was another reason for adding an alternative
mechanism (alias) in SV, however given that Verilog-AMS has not been 
integrated with SV it's preferably that simple assigns can be treated
like short-circuits in regular Verilog. 

No physical wire is unidirectional, the idea that the signal flow is 
unidirectional is a high-level concept - i.e. it hasn't got much to
do with hardware modeling, it's just syntactic sugar for the designer
and EDA tools.

Kev.