Re: gEDA: Icarus NetAssign, NetAssignNB

[Steven Wilson <stevew-at-NOSPAMintrinsix_dot_com>]

I'll take this - Steve isn't around for the moment.

This is one of those very basic confusions of verilog -

Two examples - one of each:

reg a, b,c ;

// Assume that we start at before the clock with a = 1, b = 0, c = 0.

always @ ( posedge clk)  // Blocking
  begin
       b = a;
       c = b;
   end

always @(posedge clk) // Non-blocking
  begin
    b <= a;
    c <= b;
  end

So what is the difference -   after the rising clock edge occurs -

Blocking: a = 1, b = 1, c = 1.
Non-blocking a = 1, b = 1, c = 0.

Why?

Well - blocking means wait till the current step is completed before 
moving to the next statement. Non-blocking means perform all statements 
in parallel.  

Applying these definitions to the examples we find that in the blocking 
code. First the value of a is assigned to b, then the value of b is 
assigned to c. Thus the value of a propagates to both of the other 
variables.

In the non-blocking case, the value of a is ONLY assigned to the first 
statement, while the current value of b is assigned to c SIMULTANEOUSLY.

As a coding convention - a way to keep out of trouble is to use Blocking 
ONLY for combinational logic (think muxes..) while you only use 
non-blocking for describing registered logic.  So anywhere you have a 
"posedge/negedge" in the always statement - no blocking code.

Hope this helps.

Steve





Hendrik Greving wrote:

> Hendrik Greving wrote:
>
>> Hi,
>>
>> I'm Hendrik, new to this group.. Currently, I'm working with Icarus 
>> and modifying it according my purpose. I've got a short question, 
>> could anybody tell me, what's the difference between above?
>>
>> Regards,
>> Hendrik
>>
>>
> blocking/non-blocking?
>
> Regards,
> Hendrik Greving