Re: gEDA: Iverilog : problems with real numbers

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

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Dan McMahill wrote:
> Stephen Williams wrote:
> 
>> If you are just looking to pass the voltage value out of the module
>> for display purposes, then Icarus Verilog also adds the extension of
>> allowing you to declare wires as real-valued. Unfortunately, there's
>> another bug in that the port declarations of real wires doesn't seem
>> to work yet, so that's another bug for the database:-)
> 
> Does that mean you could also pass a real into a module?  Is this an
> Icarus Verilog only feature or do you know if it's something that
> commercial tools would do too?  This would seem to be an extremely
> powerful tool.

That's the idea, yes.

And yes, it is a language extension. SystemVerilog may have it as
it is based on a Cadence proposal to the Verilog and SV groups.
In fact in Icarus Verilog you can have logic and bool vectors, and
real values. All of these things I expect to be able to pass around
nets (including ports) like any other logic. If you see any bugs
there, file it as a bug report not a feature request.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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