Re: gEDA: Iverilog : problem with $setuphold on bus signal

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

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The best place to submit concise bug reports like this is in the
bug reports system, here: <http://icarus.com/eda/verilog/bugs.html>

And incidentally, you don't say what you mean by "pass" for "fail".
I'm guessing you mean that it doesn't compile. It would help a lot
if you would submit this to the bugs system with a short, complete
example.

Thanks,

Steven Kwan wrote:
> Hi Steve and all,
> 
> I tried on 2 different versions (0.8 & 20060409) and found the following problem.
> Both failed to compile.
> 
> 
> ==================================================
> 
> wire D_7 = D[7];
> 
> 
> ...
> 
> 
> // fail
> $setuphold(posedge TCK &&& XMG, negedge DIN[7], 0, 0,
> notifierX24,,,TCK_X, D[7]); // fail
> 
> // pass
> $setuphold(posedge TCK &&& XMG, negedge DIN[7], 0, 0,
> notifierX24,,,TCK_X, D_7); // pass
> 
> ==================================================


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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