gEDA-dev: Re: iverilog: Reduction OR follows bitwise OR operator

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Stephan Boettcher wrote:
> Hi Steve,
> 
> The following code runs fine on iveriog, but some synthesizers
> complain about it:
> 
>    wire      next;
>    reg [1:0] worda;
>    wire      read = next | |worda;
> 
> Is there an issue with the relevant standards, with some opportunity
> for a warning by ivl?

There is no ambiguity. || is one token, and | | are two tokens.
I see no way that a reasonable parser would be able to confuse
this with logical or (||). The point of the warning might be to
catch typos, though.

> Cheers
> Stephan
> 
>>    reg [1:0] 		worda;
>>    wire 		read = next | (|worda);     // 6-22, JC
>>
>> // Compile ERROR:  Reduction OR follows bitwise OR operator, consider using brackets to disambiguate.
>> //   wire 		read = next | |worda;     // 6-22, JC
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-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

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