gEDA-dev: Re: gEDA: Iverilog : problem with real number

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

OK, I've checked into CVS some changes that should take care of
this. Real numbers in this context (and others) should work fine.

Steven Kwan wrote:
> Hi Steve and all,
> 
> 
> Just installed snapshot 20060618 and 
> tried to compile pll_model.v (attached).
> 
> Problem on line 63.
> 
> /////////////////////////////////////////
> 
> assign #(6*vcoClkHalfPeriod) resetDoneDelayed = resetDone; // line62 :
> compile pass
> assign #(6.0*vcoClkHalfPeriod) resetDoneDelayed = resetDone; // line63 :
> compile fail
> assign #(test) resetDoneDelayed = resetDone; // line64 : compile pass
> 
> /////////////////////////////////////////
> 
> 
> 
> [kk@spl2]$ iverilog -tnull pll_model.v
> pll_model.v:63: error: Real constants are not synthesizable.
> sh: line 1:  3417
> Done                    /eda/iverilog-20060618/lib/ivl/ivlpp -L
> -D__ICARUS__=1 -f/tmp/ivrlg2c4caf8c
>       3418 Segmentation fault      | /eda/iverilog-20060618/lib/ivl/ivl
> -C/tmp/ivrlh2c4caf8c -C/eda/iverilog-20060618/lib/ivl/null.conf -- -
> 
> 
> 
> [kk@spl2]$ iverilog -V
> Icarus Verilog version 0.9.devel ($Name: s20060618 $)
> 
> /////////////////////////////////////////
> 
> 
> 
> Thank you for your support.
> 
> Best regards,
> Steven.
> 
> 
> 
> ------------------------------------------------------------------------
> 
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-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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