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Re: gEDA-dev: Blind and buried vias in PCB... who is doing what?
Bert,
I am not sure I understand alll of your question. Thanks for pointing
out the source document though.
Page 21 is about buried capacitance. We tend to use a lot of capacitors
inorder to prevent (have bypass) any AC signal from entering the power
pins of an active device. depending on what we are trying to occomplish
we might use between 1 and 3 capacitors per power pin. For high speed
analog we might also throw in a series resistor or inductor. The use of
all of these capacitors ends up taking up a fair amount of realestate.
What the author of the article is pointing out is that we could
construct capacitors between layers of the board and the smaller the
spacing between layers the higher the capacitance. But the thinner the
dialectric layer the less suseptable to breakdown it had better be and
you have to worry about contamination durring the board assembly process.
Shooting from the hip I would guess,
Benefits ....
elimination of bypass capacitors, fewer errors durring component
assembly process, shorter vias (blind vias) thus reduced added
inductance and resistance. Since often (on my boards) the bypass
capacitors are found on the back side they get connected to ground
planes and power planes and to the top layer by a couple of full length
vias. This would be reduced to a single blind via. opening up even more
realestate.
Problems....
contamination, breakdown in dialectric material
Part 2) I think looking at the technology capabilities for one fab shop
will give us a clue
http://hunterpcb.com/text/41/192/
Under the advanced production capability column see the entries for rows
Min. Outer Layer Via Land Size and Min. Inner Layer Via Land Size.
For the outer the minimum is 18 mills for the inner the minimum is 16 mills.
I don't know why but I do know who to ask and so I will. But the
interesting thing is that the inner layer can take a smaller pad size
then the outer layer opening up more realestate for traces.
One last thought,
>From my experience the high end PCB fab shops modify the gerber files
that you give them. With your permission of course, they will change the
shape of the via land patterns to tear drop from round. They will
calculate the trace thickness and adjust trace width depending on
desired impedance. They will help you with material and finish
selection... In short they should know their job. For complex, high
frequency boards I strongly recomend you select a shop early and work
with them from the start of the board layout.
Steve Meier
Timmerman, Bert wrote:
>Hi Steve and all,
>
>Has someone on the list ever experienced the need for "Buried
>Capacitance (TM)" (BC) for decoupling purposes.
>
>I read this the other day in a Design For Manufacturing Guidelines
>document on
>"http://www.pcblibraries.com/resources/files/GenDocs/DFM%20Guidelines.zi
>p" page 21 and page 62 for Blind/Buried Vias (BBV).
>
>Would the BC require the use of widened traces/rectangles/polygons in
>"footprints" on the inner layers ?
>
>And then there is the issue of padstacks: dimensions of top-pad,
>inner-pad and bottom-pad are allways equal in the current implementation
>of vias/plated through mounting holes (not to mention the
>anti-pad/clearance on those layers), curently there isn't a proper way
>to implement these features in the file format.
>
>If the file format of the pcb files is to be altered to accommodate for
>BBV etc. then this may also be of interest to you.
>
>Just my EUR 0.02
>
>Kind regards,
>
>Bert Timmerman.
>
>-----Original Message-----
>From: geda-dev-bounces@moria.seul.org
>[mailto:geda-dev-bounces@moria.seul.org] On Behalf Of Steve Meier
>Sent: Sunday, July 16, 2006 12:12 AM
>To: gEDA developer mailing list
>Subject: Re: gEDA-dev: Blind and buried vias in PCB... who is doing
>what?
>
>I sure could use all the way down to micro vias for my current project.
>I would also love having the ability to swap pins on these big fpga
>devices. The good news is... that the increase in layers means I can
>still get at all the pins of a 1000 and some count device even without
>blind, buried and micro vias, however I am pretty sure it would still
>help on the overal surface area requirements too.
>
>Uhm, I think I was supposed to do some research for DJ on what fab
>houses expect. So I think I am the one that has fallen doen on the task.
>
>Steve M.
>
>
>DJ Delorie wrote:
>
>>I know of no current plans to add blind/buried via support to PCB.
>>
>>
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