Re: gEDA-dev: Blind and buried vias in PCB... who is doing what?

[Steve Meier <smeier-at-NOSPAMalchemyresearch_dot_com>]

Ok, I just asked and I was told that these are recommended by IPC and
military standards... Not a very satisfying answer. Looks like I will
have to dig deeper.

Steve Meier


> 
> Part 2)  I think looking at the technology capabilities for one fab shop
> will give us a clue
> 
> http://hunterpcb.com/text/41/192/
> 
> Under the advanced production capability column see the entries for rows
> Min. Outer Layer Via Land Size and Min. Inner Layer Via Land Size.
> 
> For the outer the minimum is 18 mills for the inner the minimum is 16 mills.
> 
> I don't know why but I do know who to ask and so I will. But the
> interesting thing is that the inner layer can take a smaller pad size
> then the outer layer opening up more realestate for traces.
> 




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