Re: gEDA-dev: Thoughts on buses in gschem

[John Griessen <john_g-at-NOSPAMcibolo_dot_com>]

The state of the PCB code seems to be it can handle the Cadence style of
attaching any kind of information to any drawing object.  If that is so now,
I think the way Cadence did it is a good model that allows people to do it their
way -- put a label on a wire, or put an invisible property on it that gives it
a bus bit range, or attach it to a pin so it inherits what that pin has, and any 
wire segments inherit the properties of what they touch until you change that.

With such a style of doing busses, you could maybe create a "schematic 
component" from a set of labeled wires that branch, and it would do a bus ripper 
function.  Does gschem have a way of saving and reusing a chunk of schematic
that is only wires, and still keeps the usual functions of wires?  That would be 
a little different from a symbol, since wires need to stretch and symbols never 
do...  well...I've wanted one to... hmmm.... symbols never stretch -- yet.

John Griessen


Dan McMahill wrote:
> The way cadence handles it is all wires are basically equal and if 
> they're fat (like for a bus) or thin (like for a wire), its strictly for 
> appearance.  They way a wire becomes a bus is by labeling it or by 
> connecting to a pin which is a bus by virtue of it carrying more than 1 
> signal.


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