Re: gEDA-dev: Numerical analysis of circuit boards

[Bas Gieltjes <bas-at-NOSPAMgieltjes_dot_dds_dot_nl>]

> Have you read any papers (I suspect they exist, but I haven't looked) 
> about how tools like cadences's assura tool do capacitance extraction 

Try this link as a start:
http://ens.ewi.tudelft.nl/Publications/find_author.php?mi=4 
or google for "meijs layout extraction", I don't know if you can
download published papers. 

In the Nelsis/Ocean IC design system you can find an implementation
of the SPACE layout to circuit extractor. I might be useful as another
example.

> for IC layout?  Also I've heard that magic also has a capacitance 
> extractor.  Assura does its work by running something like fastcap over 
> a whole bunch of structures and it builds up a table.  Then it does some 
> sort of fast calculation on the actual layout using the table  and some 
> sort of interpolation.  It is done this way in an attempt to combine a 
> field solver for some accuracy with an algorithm which is fast enough to 
> be practical for a real layout.

 Bas
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