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Re: gEDA-dev: about gEDA hierarchical netlist
Hi Mike Jarabek and Everyone,
Mike, thank you very much for your valuable tips and response. In our
design environments (we design full custom VLSI chip), everything is
schematic driven all the way down to the transistor level. The
schematic systems and their netlists drive VHDL, Verilog, SILOS,
Spice(HSpice) etc, simulators, and other signal integrity and path
analysis tools, and SpiceLVS(and other formats) for Dracula LVS for
physical layout verification. Cross probings among schematic and other
tools are heavily used to ease the design and design verification
process. Logic synthesis and layout synthesis tools are used too, but
the results are always fed back to the schematic systems to satisfy the
various tools as described above. In that design environment,
hierarchical netlists are crucial, and monolithic non-flatten netlists
are common. Incremental designs are routinely done, and in the end,
the outcome depends on how soon we can get to the finish line of first
silicon success.
I took a look into the gEDA schematic system, its design is very
generic and uninhibiting to be used in all kinds of design
environments, PCB, FPGA/ASIC, Analog, VHDL/Verilog, SystemC, VLSI, etc.
And I am glad I came to the right place.
By the way, if I have some codes to share with all, or to contribute to
the gEDA development, where do I post them? Is email with attachment
allowed to be posted to the geda-dev/user mailist?
Thanks again for your response.
Best Regards,
Paul Tan
-----Original Message-----
From: mjarabek@istop.com
To: geda-dev@moria.seul.org
Sent: Sat, 23 Sep 2006 8:35 AM
Subject: Re: gEDA-dev: about gEDA hierarchical netlist
Hi,
On Sat, 2006-09-23 at 06:56 -0400, pt75234@aim.com wrote:
> Hi Everyone,
> I am new to this posting. I've been trying to find out more about
> hierarchical Verilog/VHDL/Spice netlist features in gEDA. I searched
> and found some discussions on this topic from the geda-dev May 2006
> maillist archive regarding spice's hierarchical netlist. I had also
> tried to actually run some test examples to understand the
hierarchical
> netlist feature in gEDA in general. Similar to what others had said
in
> the May 2006 maillist, my test run only got flatten hierarchical
> netlist from gEDA netlisters. So I decided to experiment and wrote a
> crude bash script to generate a non-flatten hierarchical verilog
> netlist first as a proof of concept. The script is quite simple, it
> gathers hierarchical info from sch and sym files of each hierarchy
> levels in the design, generate a unique sym/sch list and invoke
gEDA's
> gnetlist verilog to do each level of netlisting. As each level is
> processed, netlists of all hierarchical levels from different unique
> modules are concatinated into one netlist file. The script also
> generates a report file for the entire hierarchy of the design.
>
I usually use a makefile that knows how to convert schematics to
verilog/vhdl with a rule. I don't usually put the source file attribute
on my symbols so that the netlister does not recurse into the lower
levels, and generate a flat netlist.
Once I have the separate HDL files I use the project file or manifest
file features of the simulator or synthesis tool to link them all
together. No need to generate a giant monolithic source code file.
This also gets you incremental compilation if your simulator supports
it. (Modelsim can work this way.)
> If you are interested, I'll be glad to post the script up. Ah, I have
> yet to learn the rule of posting files here; whether I should email
it
> as an attached file, or I have to upload it elsewhere? Or is there a
> HOW-To that I can read to find out?
>
> Best regards,
> Paul Tan
>
> _______________________________________________
> geda-dev mailing list
> geda-dev@moria.seul.org
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
--
--------------------------------------------------
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--------------------------------------------------
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