gEDA-dev: Re: Icarus Verilog and Xilinx unisim files

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Uwe Bonnes wrote:
> Dear Stephen,
> 
> thanks for the fixes for my recent reports. Now I want to run the top level
> of my design that instantiates a block ram. This hits another assertion.
> 
>> iverilog -o /tmp/a.out RAMB16_S9_S36.v ../glbl.v 
> ivl: eval_expr.c:1660: draw_select_signal: Assertion `0' failed.
> sh: line 1: 32620 Done                    /usr/local/lib/ivl/ivlpp -L -F/tmp/ivrlg2e76bb53 -f/tmp/ivrlge76bb53
>      32621 Abgebrochen             | /usr/local/lib/ivl/ivl
> -C/tmp/ivrlhe76bb53 -C/usr/local/lib/ivl/vvp.conf -- -
> 
> Are you interested in those kind of reports too? Should they be checked into
> the bug database?
> 
> You can get access to the Xilinx unisim file by downloading Xilinx ISE
> Webpack for free. I guess however, you already have access to ISE.

I do want those types of bug reports, and I do use Xilinx unisim
libraries in my day job regularly. Note that they are sometimes a
moving target (they change from ise version to version).

> B.t.w, is there a way to run iverilog in the debugger? A backtrace at the
> point where the assertion is hit might help to fix (or work around) bugs
> myself.

If you're building from source, one easy thing you can do is see
the assert in eval_expr.c line 1660 and replace it with an ivl_assert
that will give a Verilog file/line number as well. That may help you
narrow down the problem. But if you can't, that's OK to. Just make
sure I have the version information I need.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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