Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Wednesday 21 March 2007 15:38, Stephen Williams wrote:
> There is also, dare I say it, EDIF. The big vendors may have
> botched their use of EDIF, but it does have the advantage
> that it reflects netlist, and also other information like
> schematics information.
>
> It is also easier to parse. VHDL is simple on the surface but
> a VHDL parser gets very complicated very quickly.

EDIF has a Lisp like syntax.  contrast .. VHDL has a ADA like 
syntax, Verilog claims to have a C like syntax, but botched it.  
It's more like PL-I, and somewhat inconsistent.

So, yes, EDIF is easier to parse.  Parsing is a tiny piece of 
the whole problem.

How do you do the entity/architecture concept with multiple 
architectures?

How about behavioral modeling?  Remember ..  this is for an 
interchange format, hopefully no more than one step away from 
lots of native formats.  Behavior is one of them.   Can you 
make a lossless transformation from Verilog to EDIF and back?

What applications use it as native?  I am not aware of any 
analog/mixed-signal simulators that use EDIF as the native 
language.

I believe it is possible to make a lossless transformation from 
full Verilog-AMS to VHDL-AMS and back again.  Remember, for a 
common interchange format, it must be possible to make a 
lossless transformation from any native format to the 
interchange format, and back to the original.


_______________________________________________
geda-dev mailing list
geda-dev@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev