Hidden Nets Re: gEDA-dev: New diagram (attempt at UML)

[Steve Meier <smeier-at-NOSPAMalchemyresearch_dot_com>]

This subject has come up a few times.

Traditionaly gaf has allowed symbols to have net attributes. Common ones
are net=VCC or net=gnd. These attributes are typically not visible,
which is why I call them hidden.

Because power issues have become more complex... What is the voltage
level of VCC? Some times 5V and some times 3.3V and many many devices
now have multiple power pins I have added to my stuff the concept of a
somewhat hidden net. A hidden net traditionaly joins into a single net
all these hidden (non graphical) pins along with what ever graphical
pins are attached some how to the same net.

In my code, I allow the hidden net attribute. But if the device has one
of the pins in the hidden net as also a graphical pin then rather then
associating that hidden net with a schematic level net I make that
hidden net become connected to whatever net is connected to the
graphical pin.

A third use was proposed by DJ and I intend to implement it, is for BUS
pins on symbols (complex) to have a list of pins associated with it.
Then each pin gets attached to a net from the bus in the order of the
bus attribute and the order of the pin in the more then likely hiden
list of pins.

I stated:

I don't support the slot concept for buses I am not sure their is
a need since I expect symbols that have busses are just graphical
constructs that must have attached schematics

DJ responded:

"RAM chips.  My original purpose was to avoid having dozens of pins on
a symbol, since that bloats the size of the symbol.  The spec sheets
usually just have a bus line coming out of the chip's symbol."



_______________________________________________
geda-dev mailing list
geda-dev@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev