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Re: gEDA-dev: New diagram (attempt at UML)



On Thu, 2007-03-22 at 17:42 +0000, Peter Clifton wrote:

> 
> > struct st_complex {
> > 
> >   char *basename;
> > 
> >   BOOL is_hierarchy_io;    // is this an interpage hierarchical symbol?
> >   BOOL is_schematic_sym;   // is this a symbol that has a schematic?
> > 
> >   DISPLAY *display;   // how object relates to world and display window
> > 
> >   BOOL embeded;
> > 
> >   GList *net_pin_objs;         // list of net pins
> > 
> >   GList *bus_pin_objs;         // list of bus pins
> > 
> >   GList *hidden_nets;          // list of nets
> > 
> >   GList *prim_objs;            // Other Primitive objects 
> > };
> 
> Looks good. I'm thinking that for the diagram we produced:
> 
> net pins and bus pins "might" be the same object. At least, derived from
> the same object.
> 
> The list of hidden nets is unimportant for a graphic representation.
> That should come under the circuit model.
> 
> Regards,

>From my perspective, what I need today, is the netlister that handles
hierarchical buses and hidden nets and so forth.

I havn't worried too much about display issues since the netlister has
had a fairly static view. The schematic being static before being fed to
the netlister. But as I have started working on regenerating libgeda I
am now starting to puzzle on these... This would be a Good time for our
local hid expert to jump in and tell me what to do.

The two pin lists are in my implementation just lists of OBJECT
pointers. Yes the object type for each of these is PIN. The only
difference is in the PIN data structure you can define a pin_type value
that tels you if it is a bus pin or a net pin.

Steve Meier



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