gEDA-dev: Re: VHDL as a file format

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Evan Lavelle wrote:
> al davis wrote:
>> On Tuesday 20 March 2007 21:24, Stephen Brickles using shaun wrote:
>>> I am curious - what would a symbol representation look like
>>> in VHDL ? Based on what you are proposing, you would need to
>>> be able to describe drawing objects like lines, arcs and
>>> circles in this language... Is this possible in VHDL ... or
>>> did I miss something here ?
>>
>> Simple answer: Yes, it will do that.
> 
> Hang on. I haven't been following this thread, but there does seem to be
> some idea that VHDL can be used as a "schematic" representation. It
> can't - it codes point-to-point connectivity, but it can't code any
> spatial or geometric information about *how* the connection is drawn
> (arcs, straight lines, unrouted rats nest, routed, whatever). VHDL and
> Verilog don't do this. You have to go to a much lower level (GDSII,
> OASIS, etc) to get this information.

He's not actually proposing to use VHDL but to steal some syntax
from VHDL and interpret it as he sees fit for the task. In particular,
he's only interested in the entity-architecture separation. In other
words, he's defining a new set of semantics for (parts of) an
existing syntax.


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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