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Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS

Hi,

  Attaching named attributes to instantiations in the Verilog netlister has been on my todo for a long time. I will add this. 

  I will look more into the special ground node naming, this is something I have not seen before. But likely because I have never used Verilog-AMS. I don't see any difficulty in creating a special symbol to denote this kind of net and teaching the backend to handle it. I will investigate. 

Mike
--------------------------------------------------
                                      Mike Jarabek
         FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek                    
--------------------------------------------------  

-----Original Message-----
From: al davis <ad136@freeelectron.net>
Date: Fri, 23 Mar 2007 13:51:07 
To:geda-dev@moria.seul.org
Subject: Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS

On Friday 23 March 2007 09:34, Stuart Brorson wrote:
> It would be interesting to see your test schematic.

Let's see if this works ..  "attach ...."

Please don't tell me what I need to do to make it work.  I know 
what changes will make it work.  I offer it as an example of 
something that people expect to work, and doesn't.

I have been using gschem, gnetlist, gnucap for years, many 
times.  I know how to work around the limits.  I'm trying to 
remove the limits and eliminate the need for such work-arounds.

and also provide a way to simulate from a layout, a gerber,  ...  
to check matching between files, to verify, to spawn new tools 
we don't have yet.



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