Re: gEDA-dev: Regarding SoC application

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Friday 23 March 2007 13:07, Lars Johannesen wrote:
> I would like to apply for SoC for the gEDA project, but was
> curious if I could get some help with my application ?
>
> Short text on myself:
> I'm a fourth semester student at the university of Aalborg
> with major in Health and Science technology (a mix of
> electronics, programming, biology, and to some extent
> physics). Previous semesters I've used SPICE to simulate
> analog circuits for our project, which was an attempt to
> measure brain activity with light.
> This semester we work mostly with digital electronics, but as
> last semester we had problems finding a good project to do
> the circuit design in, because we needed to print our circuit
> layout and figures throughout our report.
>
> Which is what makes me interested in applying for the gEDA
> project :) I have experience with C programming and some C++
> programming.
>
> I think the improvement of the simulation part of gEDA
> (Usability improvements for ngspice/Gnucap), also I think it
> could be nice to have a win32 version of gEDA - mostly
> because a lot of my fellow students at the university runs
> win32 and frequently asks me if I know any decent programs
> for designing circuits in.

The biggest most important need for the simulation part is to 
redo the translation system according to the VHDL (could be 
Verilog) proposal I made.  I will be your mentor if you want.  
This could be a good SoC project, and it will have high 
visibility.  It takes gEDA into an area where it has not yet 
been.

There are texts that would include gEDA and gnucap if we can get 
this working well enough.

Another place where I need help is with the windows port of 
gnucap.  This is not a SoC project.  I don't have a Windows 
system, and with the new use of plugins I don't know what 
happens on Windows.  I am not likely to do it myself because 
there is so much other work to do.

There is also the possibility of a version of gnucap without 
plugins, for windows, if we can't get plugins to work.  I guess 
that would be like the "crippled demos" you often get in texts.

I think your friends are hurting themselves by learning only 
windows, but that's their choice.

Back to the translator ...  The biggest problem with the 
simulation environment has been the incomplete translation from 
schematic to netlist.  WIth the growth in gnucap capability, 
there is a growing gap between the capabilities of both gnucap 
and gschem, and what gets translated.  There is also a need for 
simulating from layout, from gerber, and other sources, and 
sharing and relating between them.

Gnucap will be using primarily  VHDL-AMS and Verilog-AMS as 
input languages, with Spice only for compatibility to read 
legacy files.  

One benefit of the *AMS languages is that they can be used to 
express and model just about anything.  This opens up new needs 
in the schematic and translators, hence the need for the new 
translators.

So that's my recommendation for a project.  I will come up with 
details if someone will do the coding.

Even if SoC doesn't accept, I still need the help.


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