Re: gEDA-dev: New diagram (attempt at UML)

[John Doty <jpd-at-NOSPAMwispertel_dot_net>]

On Apr 9, 2007, at 9:03 AM, Peter Clifton wrote:

> It thus makes (some) sense to have a "circuit" file, which lists the
> page files making up one circuit. This also makes a good place to put
> toplevel attributes for this circuit.

One problem is that when you are netlisting a hierarchy, you need to  
know when to stop, and that depends on the purpose of the netlist,  
not on the design itself. When making a netlist for board layout, the  
netlister should stop descending when it sees a footprint (so it  
doesn't try to expand an internal simulation schematic). On the other  
hand, a model should stop a simulation netlister. Remember that one  
might, for simulation purposes, model subsystem behavior above the  
level of parts with footprints. Or in IC design, your parts won't  
have footprints. So there isn't necessarily just one list of pages.

John Doty              Noqsi Aerospace, Ltd.
jpd@noqsi.com




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