VBS
Verilog Behavioral Simulator
ChangeLog
What is VBS?
This is the public release of the Verilog Behavioral Simulator.
Verilog is a Hardware Description Language used mostly for digital circuit
design and simulation. This program is a simple implementation of a
Verilog simulator. VBS tries to implement all of the Verilog behavioral
constructs that are synthesizable, but still allow complex test vectors
for simulation.
Please send all comments/suggestions directly to Jimen Ching.
(e-mail is listed below.)
What are the latest features in the current release?
What's New in 1.4.0
This release contains many bug fixes and a few new features. The new
features include:
Shell interface for Guile
$dump* API support
Multiple/lvalue concatenation
Net declaration assignment
Delay or event control in non-blocking assignment
Hierarchical variable reference
There are too many bug fixes to list here. VBS now passes many of the
test cases in the IVL test suite maintained by Steven Wilson. The
Makefile includes a target to run through those test cases. The test
suite can be downloaded from the Icarus project; icarus.com.
What does it look like?
There are no screenshots at this point. VBS is a text/command
line program.
Who is the author of VBS?
Jimen Ching
jchingATflex.com
The official website is at:
http://www.flex.com/~jching
What is the current version?
1.4.0
Where can I download it?
VBS is developed and distributed seperately
from the gEDA tarball.
You can download it from
ftp://ftp.geda.seul.org/pub/geda/dist
or
http://www.geda.seul.org/dist
You can also get the latest version from the official homepage at:
http://www.flex.com/~jching
